1. Field of the Invention
This invention relates generally to fabrication of semiconductor devices, and more particularly, to a method of fabricating flash EPROM or EEPROM memory devices.
2. Discussion of the Related Art
U.S. patent application Ser. No. 09/283,308, entitled BARRIER LAYER DECREASES NITROGEN CONTAMINATION OF THE PERIPHERAL GATE REGIONS DURING TUNNEL OXIDE NITRIDATION, filed Mar. 31, 1999, invented by Yue-Song He et al., now U.S. Pat. No. 6,143,608, hereby incorporated by reference, shows and describes a method for avoiding nitrogen contamination of peripheral gate regions during formation of EPROM and EEPROM memory devices. Several steps representative of that process and relevant to the current invention are shown in FIGS. 1 and 2.
As shown in FIG. 1, as part of a LOCOS process, a semiconductor structure 20 includes a silicon substrate 22 having spaced-apart field oxide regions 24 formed thereon, with sacrificial oxide layers 26, 27 formed on and overlying the surfaces of the silicon substrate 22 between the adjacent field oxide regions 24. The region 28 defines a core region where a core device, i.e., a memory cell, is to be manufactured, while the region 30 defines a peripheral region where other devices necessary for the operation of the overall structure, such as peripheral transistors and amplifiers, will be formed
A nitride layer 32 is deposited over the resulting structure, and a layer of photoresist is provided over the nitride layer and patterned as shown at 34' in FIG. 1. Next, a dry etch step is undertaken, removing the exposed portion of the nitride layer 32, with the patterned photoresist 34' acting as a mask (FIG. 2), leaving nitride layer portion 32 overlying the peripheral region 30. Subsequently, the photoresist 34' is removed, sacrificial oxide layer 26 in the region 28 is removed by wet etching using HF acid, and a tunnel oxide is grown on the exposed silicon. Then, a nitridation step of the tunnel oxide is undertaken, to improve reliability of the tunnel oxide, as is well-known. During this step, the remaining nitride 32' overlying the peripheral region 30 provides protection of the underlying area of silicon from nitrogen contamination.
Typically, in such a process, the sacrificial oxide 26 is on the order of 400 angtroms thick. However, as process and product development continue, and devices continue to be reduced in size, modern processes may require a sacrificial oxide thickness on the order of for example 100 angstroms.
As is well-known, the typical dry etch process used for removing the nitride layer 32 also removes some of the sacrificial oxide layer 26, since the dry etch process is not highly selective. With the sacrificial oxide layer 26 on the order of only 100 angstroms thick, it is difficult to protect the surface of the silicon beneath the sacrificial oxide layer 26 during that etch step, which leads to undesirable damage to the silicon lattice, in turn leading to problems in formation and operation of the memory device.
Additional problems arise when the device is a silicon trench isolation (STI) structure. FIG. 3 illustrates a structure 40 similar to that shown in FIG. 1, but showing an STI structure 40 rather that a LOCOS structure. A silicon substrate 42 has spaced apart oxide regions 44 formed therein, with sacrificial oxide layers 46, 48 provided on and overlying the exposed surfaces of the silicon between adjacent oxide regions 44. Again, the region 50 is a core region where a memory cell will be formed, and the region 52 is a peripheral region where peripheral devices will be formed. A nitride layer 54 is deposited over the structure thus far described, and a layer of photoresist is patterned as shown at 56' in FIG. 3, leaving exposed a portion of the nitride layer 54 over the core region 50, all as described above with reference to FIG. 1. Similar to the above, a dry etch step is undertaken to remove the exposed portion of the nitride layer 54 (FIG. 4), with the patterned photoresist 56' acting as a mask, leaving nitride layer portion 54' over the peripheral region 52. Again, with the sacrificial oxide 46 being very thin the problems described above with regard thereto arise here also.
It will also be noted that the thickness of the nitride layer 54 over the corner regions 58, 60 where oxide and silicon are adjoined is substantially greater than that over the sacrificial oxide layer 46 (FIG. 3).
With the dry etch being anisotropic, an incomplete etch of the nitride layer generally results, leaving what are referred to as nitride "stingers" 62, 64 in the corner regions 58, 60 (FIG. 4), which can lead to device operation problems. Continuing the dry etch to remove the stringers results in increased consumption of the (initially thin) sacrificial oxide layer 46, increasing the problems described above with regard to the damage of the silicon therebelow. If the thickness of the sacrificial oxide is increased (as at 46A in FIG. 5) in an attempt to deal with this problem, after removal of the nitride stringers 62, 64 by overetch (FIG. 6), when wet etch using HF acid is undertaken to remove the remaining sacrificial oxide layer, some of the adjacent areas of the field oxide regions 44 may also be etched away, causing a corner tinning effect, wherein steps 66, 68 are formed at the intersections of the silicon and the field oxide regions 44 (FIG. 7). This exposes side surfaces of the silicon with a crystal orientation other than (100), while the crystal orientation of the top surface of the silicon is (100), leading to device operational problems in the completed product.
While wet etching of a nitride layer using hot phosphoric acid, rather then dry etching, is a known and effective process, the photoresist used as a mask for the nitride etching step cannot stand up the high temperature and aggressive etch rate involved, leading to failures in the photoresist mask during the wet etching step.
Therefore, what is needed is a process for properly removing the portion of the nitride layer overlying the core region, meanwhile overcoming the problems cited above.